In some data communication arrangements, no separate clock signals are transmitted. This then requires recovering the clock at the receiving end in order to then recover the data. This can be characterized as the problem, in digital communications of, transferring digital signals between multiple clock timing domains. Multiple clock timing domains include the clock timing domain of a transmitting device as well as the clock timing domain of a receiving device. It is not unusual to transmit digital signals between clock timing domains having nearly the same underlying frequency clock, but different or varying phases with respect to each other.
One such arrangement is the Universal Serial Bus (USB). The USB is a bus having electrical, mechanical, and communication characteristics that follows a protocol defined in “Universal Serial Bus Specification” Revision 2.0 published Apr. 27, 2000, by Compaq Computer Corporation, Hewlett-Packard Company, Intel Corporation, Lucent Technologies Inc, Microsoft Corporation, NEC Corporation and Koninklijke Phillips Electronics N.V. The USB Specification provides a standardized approach for component interconnection and data transfer.
From the digital communications perspective, a USB transmitting device sends data in the form of packets over a USB cable to a USB receiving device with the clock signal of the transmitting device being used when encoding digital information. Packets include a defined sync field having multiple bits with a transition for each bit (i.e., from a logic 1 to a logic 0 or vis-versa), a payload with data information, and an end of packet field. As discussed below, the sync field with its transition for each bit, provides a rich set of edges for the USB receiver lock onto the phase and frequency of the USB transmitting device. The USB Specification does not allow for a separate clock signal to be transmitted and this makes it difficult for a USB receiving device to adequately recover the clock signal of the USB transmitting device.
The same problem of synchronization exists in other systems. One manner of dealing with that problem is described in “A 0.5-μm CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling,” IEEE Journal of Solid-State Circuits, VOL. 33, No. 5, May 1998. A plurality of samples are taken over each bit time. The samples are used to determine exactly where bit transitions take place. This is done, for example, with decision logic utilizing exclusive OR gates to which adjacent samples are coupled. Once edges are detected, a phase picking algorithm is used to pick the center sample.
However, single sample glitches in the sampled data can make it difficult to accurately detect edges. If the edges can not be accurately detected, it becomes impossible to locate the center sample.
A need, therefore, exists for a technique of filtering the over-sampled data before it is fed to an edge detector to overcome the problem of single sample glitches.